The present invention relates, in general, to flash memory devices and, more particularly, to a method of manufacturing a Silicon/Oxide/Nitride/Oxide/Silicon (SONOS) type flash memory device.
In general, a cell transistor of a flash memory device has a stacked gate structure. The stacked gate structure has a structure in which a tunnel oxide layer, a floating gate, an inter-gate insulating layer and a control gate electrode are sequentially stacked over a channel region of the cell transistor. In contrast, the gate of a SONOS type flash memory device has a structure in which an oxide layer forming a direct tunneling layer, a nitride layer for storing charges, an oxide layer used as a charge blocking layer, and a conductive layer used as a control gate electrode are sequentially stacked.
Differences between the conventional flash memory and the SONOS flash memory are as follows. First, in terms of the structure, in the conventional flash memory, charges are stored in a floating gate formed from polysilicon, whereas in the SONOS type flash memory, charges are stored in a nitride layer. In other words, the conventional flash memory is disadvantageous in that the retention time of charges is significantly reduced even if minute defects exist in the polysilicon of the floating gate. However, the SONOS type flash memory is advantageous in that the sensitivity to defects is relatively small in terms of the process since the nitride layer is used instead of polysilicon as described above.
Further, the conventional flash memory is limited when implementing a low-voltage operation and a high-speed operation because a tunnel oxide layer of 70 angstroms or more in thickness is used under the floating gate. However, the SONOS type flash memory can easily implement a low-voltage, low-power and high-speed operation because a direct tunneling oxide layer is used under the nitride layer.
Meanwhile, the SONOS type flash memory device has a “dual gate insulating layer structure” in which the gate insulating layer of the cell region is formed to have an Oxide/Nitride/Oxide (ONO) structure and the gate insulating layer of the peri region is formed to have a single silicon oxide layer structure. Furthermore, transistors of a memory cell region and a Drain Select Line/Source Select Line (hereinafter, referred to as “DSL/SSL”) region, included in the cell region, are formed at the same time for the simplicity and convenience of the process. Accordingly, the gate oxide layer of the transistor formed in the memory cell region and the DSL/DDL region is formed to have an ONO structure. However, if the ONO structure is used as the gate oxide layer of the transistor formed in the DSL/SSL region, the characteristics of the transistor are degraded because the threshold voltage increases.